The present invention relates to line drivers in digital systems. More specifically, the present invention relates to a line driver with programmable slew rates.
As the speed of digital circuits, such as field programmable gate arrays (FPGAs), microprocessors, and memory circuits, has increased, signal quality becomes ever more important. Generally, as the speed of a digital circuit increases the slew rate i.e. the rate a signal transitions from logic low to logic high or from logic high to logic low also increases. However, very fast slew rates can result in a variety of problems, such as overshoot, undershoot, and ringing.
FIG. 1(a) shows an idealized signal 110 having a rising edge 111 and a falling edge 117. Specifically, rising edge 111 occurs at time t1 and falling edge 117 occurs at time t2. In idealized signal 110, rising edge 111 occurs instantaneously and stops at the logic high voltage Vcc. Similarly, falling edge 116 occurs instantaneously and stops at 0 volts (i.e. the logic low voltage).
FIG. 1(b) shows a realistic high slew rate signal 120. High slew rate signal 120 has a rising edge 121 and a falling edge 126. When a driver with an output waveform like high slew rate signal 120 drives one end of a transmission line, such as a printed circuit board trace connecting the driver to other circuits, the signal voltage tends to overshoot logic high voltage Vcc during rising edges and undershoot ground on falling edges. Thus, an overshoot peak 122 occurs at the end of rising edge 121. Then, as high slew rate signal 120 is brought back towards logic high voltage Vcc an undershoot valley 123 occurs as shown in FIG. 1b. These overshoot peaks and undershoot valleys, known as ringing, may occur several times at each transition before high slew rate signal 120 settles at logic high voltage Vcc. The line driver driving high slew rate signal 120 also tends to undershoot the logic low voltage (i.e. 0 volts) during a falling edge. Thus, an undershoot valley 127 occurs at the end of falling edge 126. Then, as high slew rate signal 120 is brought back towards the logic low voltage (i.e. 0 volts) an overshoot peak 128 may occur.
Overshoot peaks and undershoot valleys in signal transitions may cause a variety of problems. For example, a very large overshoot peak or undershoot valley may cause high slew rate signal 120 to reach a voltage beyond the safe operating range of the digital circuit, which may permanently damage the digital circuit. Signal integrity may also be compromised. For example, a device receiving high slew rate signal 120 may interpret undershoot valley 123 as a transition to logic low followed by a transition to logic high.
As is well known in the art, overshoot and undershoot problems can be reduced by proper impedance matching and controlling slew rate. Practical systems with good impedance matching may still present an imperfect match so the overshot and undershoot is further reduced by reducing the slew rate of a line driver. FIG. 1(c) illustrates a slow slew rate signal 130 having a rising edge 131 and a falling edge 136. Rising edge 131 transitions from logic low to logic high at a slower rate than rising edge 121. Similarly, falling edge 136 transitions from logic high to logic low at a slower rate than falling edge 126. As illustrated in FIG. 1(c), even with a slow slew rate an overshoot peak 132 and undershoot valley 133 may follow rising edge 131. Similarly, an undershoot valley 137 and overshoot peak 138 may follow falling edge 136. However, by lowering the slew rate the magnitudes of the overshoot peaks and undershoot valleys are greatly reduced. Thus, likelihood of damage due to excessive overshooting or undershooting is minimized. Furthermore, the likelihood that a circuit receiving slow slew rate signal 130 would misinterpret an overshoot or undershoot as a signal transition is greatly reduced. Additionally, cross talk coupling between adjacent signals is related to the rate of the rise and fall times in an inverse linear fashion. By lengthening the rise time by a factor of two, the cross talk is also reduced by a factor of two.
Several well-known techniques are used to slow the slew rate of a line driver. For example, some line drivers are formed using a cascade of pull-up and pull-down devices that are activated in sequence to provide gradual transitions. However, conventional methods are generally limited to a single slew rate for a given line driver or a very limited number of preselected slew rates. Conventional line drivers are acceptable for devices designed to operate at a specific frequency. However, for devices such as FPGAs which may operate at a wide range of frequencies, a single slew rate may unduly limit the operating range of these devices. Ideally, the slew rate should be configurable and should be based on the clock period of a clock signal driving the device. Hence, there is a need for a method or system to provide line drivers having configurable slew rates.
Accordingly, line drivers using the principles of the present invention can provide variable slew rates based on the clock period of a clock signal. Specifically, the line driver has a slew rate that is a desired fraction of the clock period. Furthermore, the line driver can include compensation for temperature, voltage and process variations.
In accordance with one embodiment of the present invention, a clock period of the system clock signal is equal to a clock period reference number multiplied by a base delay of a delay line. A slew rate is set as a percentage of the total length of the period. For example, if the time period is 10 ns, choosing 20% as a settable option would result in setting a 2 ns rise time and a 2 ns fall time. A pull-up/pull-down controller adjusts the slew rate of the line driver to be equal to the specified number of base delays.
Specifically, the input signal of the line driver is coupled to a delay line. The delay line generates a plurality of delayed input signals. The delayed input signals are sequential, with each delayed input signal being delayed one base delay from the previous delayed input signal. The pull-up/pull-down controller receives the plurality of delayed input signals, and selectively applies one or more of the delayed input signals to a controlled pull-up circuit and a controlled pull-down circuit. The controlled pull-up circuit pulls the output signal of the driver to logic high at a slew rate which depends on the subset of delayed input signals applied by the pull-up/pull-down controller. Similarly, the controlled pull-down circuit pulls the output signal of the driver to logic low at a slew rate which depends on the subset of delayed input signals applied by the pull-up/pull-down controller.
The present invention will be more fully understood in view of the following description and drawings.